Synopsys ARC Processor Summit

At the Synopsys ARC Processor Summit, Drake Smith, SecureRF Vice President of Development, will be present Accelerating Group Theoretic Cryptography with ARC APEX Instructions. He will explain how a mathematically efficient cryptographic operation is significantly sped up using the ARC Processor Extensions (APEX) and discuss an approach using  Synopsys ARChitect, MetaWare, and Intel Quartus Prime. Attendees will see a comparison of the resulting performance metrics with APEX versus an assembly language-only implementation. The design example uses a fast, small-footprint, and low energy digital signature algorithm applicable for a wide range of IoT solutions and ideal where an ARC processor needs to securely communicate with an 8- or 16-bit device. Attendees will learn how to incorporate this and other security methods into their own ARC-based designs. SecureRF will have an exhibit and demonstration at the event.

Contact us to arrange a meeting with the SecureRF team at the ARC Processor Summit–Synopsys.