On the Path to a Secure Boot Solution for RISC-V
As the RISC-V ISA gains in popularity and more industries proceed with plans to build and deploy systems based on RISC-V technologies, the security requirements of those systems will grow. One avenue that hackers have used to exploit systems has been to modify the firmware and cause it to misbehave. For example, one of the recent vehicle hacks involved corrupting firmware in order to jump from an infotainment center to the CAN-BUS. The solution to this style of attack is a secure boot, and with minimal additions to the ISA, RISC-V can provide secure boot hooks directly.
Secure Boot
Secure boot is a self-hosted root of trust that uses a digital signature and a known, trusted, public key to protect the firmware before it loads. The RISC-V system validates the signature over the firmware using the trusted public key and will run the code only if the signature verifies correctly. If the firmware has been modified in any way, the signature validation will fail. Once this initial trusted load completes, subsequent loads can use the same process to chain the trust to additional loads.
Boot time is important and the performance of signature verification is paramount. If it takes too long to verify a signature then boot time can suffer. There are several use cases with very tight boot up time constraints. Moreover, some boot sequences may require validation of multiple signatures, adding to the overhead and making signature schemes with rapid verification even more critical.
The quantum threat
With quantum computers growing in size every quarter, the longevity of digital signatures is also a major concern. If a chip is going to take 2-3 years to develop, another 2-3 years to deploy, and then be in the field for 10-15 years, it’s well into the territory where a quantum computer will be able to crack all existing public-key technologies (ECC, RSA, DH, and DSA). Therefore, quantum-resistant digital signatures will likely be a requirement for many RISC-V secure boot solutions.
RISC-V Workshop
Derek Atkins, SecureRF’s CTO, attended the RISC-V Workshop in Barcelona, May 7-10 and presented our fast, quantum-resistant, secure boot solution for RISC-V. His presentation included requirements for a software-based secure boot solution, leveraging a trusted initial-stage boot loader; and RISC-V ISA updates that could reduce the software requirements (and thereby reduce the size of the trusted boot loader). Eventually, future ISA updates will enable a compliant RISC-V processor itself to be the root of trust and perform the secure boot process on the initial-stage boot loader, without requiring the loader to be trusted.
If you want to learn more please contact us at Info@SecureRF.com.